1. Field of the Invention
The present invention relates to logic circuit emulation systems. In particular, the present invention relates to providing data transport across practically asynchronous portions of a logic circuit emulation system.
2. Discussion of the Related Art
A typical emulation system for a large logic circuit is described, for example, in U.S. Pat. No. 5,761,484, entitled “Virtual Interconnections For Reconfigurable Logic Systems,” to Agarwal et al. Such an emulation system is often used during the development of an integrated circuit to simulate circuit operation and circuit performance. In such a system, the designer provides a logic netlist that is then partitioned by the emulation system for implementing an emulation circuit configured in a number of programmable logic devices (e.g., field programmable gate arrays or FPGAs). These programmable logic circuits (PLDs) are typically provided on one or more circuit boards in the emulation system, with each circuit board containing a number of these programmable logic devices connected in a convenient topology.
Many techniques for efficiently implementing the emulation circuit have been developed. For example, U.S. Pat. No. 5,761,484, entitled “Virtual Interconnections for Reconfigurable Logic Systems” to Agarwal et al., provides an efficient method to route signals between the PLDs by “multiplexed data transport,” i.e., sharing input or output pins among many input or output signals. In one implementation of that system, a clock signal (“virtual clock”) of many times the frequency of the system clock is used for these input and output signals. U.S. Pat. No. 5,854,752, entitled “Circuit Partitioning Technique For Use With Multiplexed Interconnections” to Agarwal, provides an efficient way of circuit partitioning that achieves high utilization of the available resources in the PLDs. U.S. Pat. Nos. 5,659,716 and 5,850,537, both entitled “Pipelined Static Router And Scheduler For Configurable Logic System Performing Simultaneous Communications and Computation” to Selvidge et al., disclose methods for efficiently routing among PLDs signals under timing constraints. U.S. Pat. No. 5,802,348, entitled “Logic Analysis System For Logic Emulation Systems” to Stewart et al., provides logic analyzer functions to be used in analyzing the operations within the emulation circuit.
In a large logic circuit, circuit operations are controlled by one or more clock signals. Thus, proper handling of clock signals is important to achieve a successful emulation of a logic circuit. For example, U.S. Pat. No. 5,649,176, entitled “Transition Analysis And Circuit Resynthesis Method and Device For Digital Circuit Modeling,” discloses using an internal clock signal outside of the timing signals of the logic circuit to control the internal operations of the emulation circuit. In a typical emulation system, a single clock signal is distributed throughout the emulated logic circuit to provide synchronization. While this clock distribution scheme is conventional in an emulation circuit configured in PLDs in very close proximity (e.g., PLDs on a single circuit board, or on different circuit boards interconnected on a single backplane bus), such a clock signal cannot be provided between PLDs separated by a relatively large distance (e.g., PLDs on circuit boards on different chassis) or at high clock frequencies, such as those used for multiplexed data transport. In such a system, there may be large clock skews at different points of the system relative to the clock period that cannot be reliably estimated. Thus, practically, those different points of the system are effectively asynchronous relative to each other. Thus, there is a need for a reliable method for transporting data between distinct asynchronous components of a system, without relying on a common clock signal distributed throughout.
Asynchronous communication can be carried out by: (a) providing explicit flow control signals, (b) embedding a clock signal in a data signal, and extracting the clock signal in a decoding circuit during decoding, and (c) providing a frequency-controlled clock signal, and encoding both data and clock phase, and reconstructing clock signal phase during decoding.